Translator



8 sheets-sheet 1 July 13, 1965 E. J. GLENNER TRANSLATOR Fled OCT.. 19, 1962 t 3J :n 2G22: R 0 n 55:2 m z3 T n n 595 ESE .qwzoo m m I .IIIII .Il II V :l III.' Il I 'III d I l L @E I C 1.9 I I. ou V14 .2: .L 22:8 B l Il lm 555mm 555; #los 525 55 E I hmm 52: 26522, 595 mz: .l 55%: ONT l I Il |I| $8.022. Suazo@ July 13, 1965 E. J. GLENNER TRANSLATOR 8 Sheets-Sheet 2 Filed Oct. 19, 1962 FROM SENDER GROUP UN |18 STORAGE ZUAR C UNITS col NclDr-:NCE

HUNDREDS COINCIDENCE 2 HCG E .m www El TCT N2 0 C BNA RY COUJTER DECODING COMMON ADDRESS COUNTER 70A INVENTOR. Edward J. Gleaner FIG. 2.

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July 13, 1965 E. J. GLENNER 3,194,892

TRANsLAToR Filed Oct. 19, 1962 8 Sheets-Sheet 5 FROM SENDER TO SENDER JRLS SIG; J

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UcA-Ucnq TCA-TCD-l HcA-HcD-f To BUFFER Ress GRPs z-io TSA\ TSBN TSC\ TSD\ DMW nauw H INVENTOR Edward J. Glenner FIG 3 BY @l Hy.

July 13, 1965 E. J. GLENNER 3,194,892

TRANSLATOR Filed Oct. 19, 1962 8 Sheets-Sheet 4 TO SENDER (ANI) 8 Sheets-Sheet 6 IN VE NTOR.

E. J. GLEN NER TRANSLATOR \V BM July 13, 1965 Filed Oct. 19, 1962 Edward J. Glenner BY V `f/ Atty | I Il fr f f r f f r D D D D D D D D t9@ iwi (F55 .w ANG N Mv Q Q @o ma E NQ E w 1 D 1. 1 l

July 13, 1965 E. J. GLENNER TRANSLATOR 8 Sheets-Shes?l 7 Filed Oct. 19, 1962 AHy.

July 13, 1965 E. J. GLENNER TRANSLATOR 8 Sheets-Sheet 8 Filed Oct. 19, 1962 T TIME OUT TOI READ

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x E 9 1D o un I, o SR S V. W 9 U w s |IM 9 lc, o VNIF v[SFO s s .E MT VIA SG A MIM w United States Patent O 3,194,892 TRANSLATOR Edward J. Gienner, Skokie, lil., assignor to Automatic Electric Laboratories, luc., Northlaire, lll., a corporation of Delaware Fiied'ct. 19, 1962, Ser. No. 231,627 4 Claims. (Cl. 179-18) The present invention relates to automatic telecommunication exchange systems generally and more particularly to electronic translating arrangements for use in such systems.

The invention is particularly but not exclusively adapted to use in automatic crosspoint telephone switching systems of the type disclosed in the co-pending application of K. K. Spellnes entitled Communication Switching System, led October 16, 1962, Serial No. 230,887, issued February 16, 1965, as Patent No. 3,170,041.

The primary object of this invention is to provide a translator for an automatic telephone system which is capable of holding a comparatively large quantity of stored information and at the same time be comparatively small in bulk.

A feature of this invention is the use of a magnetic drum storage medium.

Another feature of this invention is the arrangement of the translator whereby the directory number of a calling equipment location may be obtained from a counter external to the drum when the equipment location on the drum is found rather than as in conventional drum systems wherein both items of information are marked on the drum.

The above mentioned and other features and objects of this invention and the manner of attaining them will become apparent, and the invention itself will be best understood, by reference to the following description of an embodiment of the invention taken in conjunction with the accompanying drawings comprising FIGS. l to 8, wherein:

FIG. l isa single line call through block diagram of a system disclosing a common translator.

FIGS. 2 to 6 show a complete schematic circuit of a translator according to the present invention.

FlG. 7 is a block diagram of the functional circuit components of the translator according to the present invention.

FIG. 8 is a diagram indicating how FIGS. 2 to 6 should be arranged to obtain the complete circuit.

FIG. 9 shows in schematic form the detailed contents of box 3C of FIG. 3.

FIG. 10 shows in schematic form the detailed contents of the box titled Common Control Circuit of FIG. 5.

In the co-pending system application of K. K. Spellnes briey shown in the block diagram of FlG. 1, when a subscriber lifts the handset, the line group marker 120 goes into action first by detecting the originating call mark, identifying the calling line, and selecting an idle register junctor within the register-sender group 160. A path is then temporarily established from the calling telephone to the register junctor via the A, B, C, and R matrices. Before the subscriber can raise the handset to his ear, dial tone has been provided. The dialed digits are stored temporarily, coded, and processing is continued as these digits are passed to the translator 170, analyzed for type of call, and instructions are selected from the drum memory 173 and returned to the registersender group 160 to guide further handling of the call. Upon receipt of the remaining digits, the translator 170 returns switching instructions corresponding to the called number as stored in the drum memory. The instructions are transmitted from the register-sender group 160 via the sender and the originating junctor OI of the originating line group 110 to the group selector 130. In the group selector 130, the instructions are analyzed by the marker 160, an idle terminating junctor TI in the terminating line group is located, and a path established to that line group via the A, B, and C matrices of the group selector 130. The remaining instructions are followed by the line group marker to locate the called line terminals, select and seize a path from the terminating junctor through the C, D, B and A matrices to the called line. The terminating junctor establishes ringing, answer supervision, and talking battery for both parties when the call is answered.

Since the system is a common control operation, the markers of the line group and group selector function only to serve the assigned portion of the call processing, then release to serve other calls. The register-sender group and the translator are functioning on a time division basis and therefore are processing several calls practically simultaneously. The temporary signaling and control paths are released for further service while only the talking paths are held through the switching matrices and junctors.

The translator of this system provides semi-permanent storage used by the system to direct the extension of telephone calls in accordance with the subscriber dialed digits.

A pair of translators are provided for each 10,000 directory numbers served by the oice. Each translator of the pair shares the trafc load. One of the pair may be taken out of operation for maintenance and all traffic switched to the other without degrading service.

Each translator can be accessed from twenty registersender groups and a supervisory console on a one-at-a-time basis. The basic type of translation processed are (l) Directory number translations. The directory number of the called party is translated into switching instructions to enable the register-sender to direct the routing of the call to its destination. The switching instructions contain the equipment location of the called telephone line and the party ringing instructions.

(2) Line number translation- The calling partys line identification is translated into the calling partys directory number. The line number translations provide automatic number identification for all lines when required, for example, for ticketed toll calls.

Information storage is provided by magnetic drums on the basis of one drum per translator. Memory words are recorded on the drum surface from a supervisory console by simply typing the memory word and appropriate memory address at the console typewriter. This directory number translation can be added or existing translations altered with a minimum of maintenance effort.

Information is represented in digital form using a four bit binary coding. The drum selected will rotate at 1,800 r.p.m. with approximately 4,000 slots along its periphery. This will yield slot widths of 8.25 aseo. and a total cycle ltime of a 33 msec. The drum will have 1,000 addresses, 4 words per address. Each Word will contain from 6 to 60 bits of storage plus indexing bits. The variation in storage results from having the drum capable of storage for l0 number groups or 10,000 numbers, but implementing only as many number groups as is needed. Each number group representing 1,000 numbers requires a 6 digit translation on a binary basis yielding, 6 bits per word, X4 words per address, or 24 bits per address.

Common reset and index heads are used along with 6 digit heads for each number group implemented. A full 10,000 numbers would require 2+ (6 10) :62 heads. The approximate physical dimensions of the drum are: diameter 8-1/2", length 8". At 1,800 r.p.m. and 4,000 bits per revolution, the bit or information rate is 120 kc.

Memory words are recorded in series parallel along the axis of the drum. Each memory word consists of 24 bits, thus occupying four serial bits in each of 6 parallel 3 tracks. Ten segments along the drum axis with each segment made up of 6 tracks provides storage for 10,000 memory Words. The memory words are addressed consecutively around the drum circumference with the first 1,000 addresses located in segment ione, the second 1,000 addresses in segment two, etc;

The drum access circuitry, consists of read and write amplifiers Dl-eDe, in close proximity to the magnetic heads.

Number group operation The overall translator number group operation is as follows: Each number group is permanently assigned a thousands digit address; so that,'when a register sender group desired the service of a number group the thousands digit is the deciding factor as to Which number group we select.

The register sender group transceiver via the allotter 7A tests the particular number group for the idlev condition as indicated by the contol '7C and the thousand group select circuit 7TGS,v if busy it continues to test at each time-slot period until it becomes idle. When the register sender group transceiver finds the number group idle it marks the circuit busy and establishes a permanent connection via the seizure circuitry. The seizure circuit in turn always directs the register sender goup tansceiver back to the number group and enables the dialed units,

tens, and hundreds digit to be gated into the proper one of the access address registers 7AR1 to 7ARIP which are individual per number group. In a coincidence circuit 7CC1 to 7CC1() these digits are continuously com- -pared with the location address of the drum 7D from the address counter 7AC. When coincidence is detected in the coincidence circuit 7CC1 to 7CC1@ associated with selected access address register, signifying arrival at the drum location corresponding to the dialed digits, the stored translated information for the particular number is read out and temporarily stored in the proper one of the exit buffer registers 7BR1 .to 7BR10 individual to each number group. The ten exit buier registers are common through a thousands group gating circuit 7TGG to a common path via the allotter 7A. The register sender group transceiver then comes back to the buffer registers associated with the addressed number group via the gating circuit 7TGG for the translated information.

Automatic number idenication The storage element for automatic number identification (ANI) is the same magnetic drum used Lwith the number group circuit. Part of the control circuitry is common to all drums in a muiti-drum translator system and part of it individual to each drum. Each drum is identical so that two calls can be handled at a time, one by each ANI circuit associated with that drum.

The register sender group transceiver via the allotter 7A tests the ANI circuit for the idle condition as indicated by the contol circuit 7C. If busy, it continues to test it at intervals until it becomes idle. Whenthe transcevier finds the ANI circuit idle, it marks the circuit busy and establishes a connection tothe access registers 'ANR via the allotter and access gates.

The information from the .transceivers for ANIYconsists of the following digits:

(l) Line terminal digits (hunrreds, tens and units).

(2) Party digit plus miscellaneous information.

(3) Two group selector routing digits.

Since a given set of information canrbe found in any one of ten drum segments (each serving 1,000 numbers) or in any segment of a plurality of drums (serving a multi 10,000 number office), it is necessary to scan all segments of all drums for each call. The input signals are amplitied and the inputs put into proper form in logic circuit 7L. So that by using ten Vcoincidence circuits 701 to 7CH) fed by the logic circuit 7L fromV the register 'IANR and Via the drum allotter "DA from the segment gating circuits TDG to '7DG1ti of each drum, the input digits can be compared continuously with the information stored on any one drum; additional drums are scanned sequentially as allotted by counter 7CA and drum allotter 7DA1 to 7DAIO. When coincidence is detected, the drum address from the drum address counter ''AC (which corresponds to the directory units, tens and hundreds digits), is temporarily stored in exit registers IOR via gating circuit 'IGC along with the number of the drum segment from 7B!) Where coincidence occurs (which indicates the thousands digit) and the number of the drum Vfrom allotter counter 'CA (the selected one of which indicates the ten-thousands digit). The sender, upon addressing the ANI circuit repeatedly, receives the directory number information from the eXit registers 7OR into which the number was fed from the drum address counter 7AC and then releases the ANI circuit.

TheV magnetic drum and reading equipment are used in common with the number group translation portion although the operation of the ANI circuit is independent of the condition of the number group portion.

`Dezail cz'rcuil descriptions The following circuit description is Written using conventional terminology in the electronic art. The detailed circuits for the gates, iiip-iiops etc. used in the overall system are Well known and may for instance be obtained from R. K. Richards in Digital Computer Components and Circuits (D. Van Nostrand Co., Inc., 1957) in chapter 4. A further concise treatment of these circuits may also be found in the General Electic Transistor Manual (General Electric Co., New York, 5th Edition 1960) in chapter 11, Basic Computer Circuits, and chapter 12, Logic Busy circuit (number group) When-a register-sender group transceiver requires the service of a number group it must iirst ascertain whether the addressed number group is idle. This is done by interrogating the busy circuit of the particular number group in the following manner. This busy circuit of a number group is addressed by coincident gating of the thousands digit (sent from the transceiver) and the state of a busy fiip-flop 'in the control circuit 3C. If the Hip-flop is in the zero state indicating the number group is idle, an AND gate, will be enabled and the thousand digit code will cause a pulse to appear on the output. This in turn is coupled through an OR gate and allowed to set the busy flip-flop tothe one state, indicating the number group as busy. Setting the busy fiip-iiop to the one state disables the AND gate and inhibits any other register sender group transceiver from seizing this particular number group. A number group is held busy until the register sender group transceiver is finished with it, at which time a release signal is gated with the coded y thousands digit, and sets the busy iip-iiop back to the zero, or idle state; or until the time out circuit overrides the register sender group transceiver and sets the busy flip-flop to zero.

Seizure circuit VSince a register sender group transceiver cannot obtain its linformation from a particular number group within the initial time-slot, it must return to the number group. To do this, a one bit storage is necessary in the transceiver to remember that the particular number group addressed by the thousands group has been tested, found idle, and seized. The storage of the seizure state allows the transceiver to return to the particular number group in the following manner: When the busy flip-Hop is set one, the one output via lead 3ST feeds a pulse through the OR gate, BSZ, onto a common highway, SZH, andis fed to the appropriate seizure iiip-op by gating with the transceiver time slot. This sets the fliptiop to the one state. Since the seizure Viip-iop is common to a register sender Ygroup of 20 transceivers it is handled on a time division multiplex basis with ferrite core storage per register. The seizure iiip-op is released or set zero by a release signal from the sender of the time-out circuit.

Number group access address circuits After a transceiver obtains the services of a number group it must transfer the dialed units, tens, and hundreds digit to an access address register ZUAR, ZTAR and ZHAR for comparison with the drum location address. Since the highways from the transceiver to the number group are on a time division multiplex basis, gating of the dialed digits to the correct number group access address register must only occur after verified seizure of the number group and during the time Slot assigned to the particular transceiver. This is achieved by using the one output of the seizure iiip-fiop, signifying seizure, and the transceiver time slot mark, to enable and and gate which in turn is gated onto a common highway and used to enable the thousands number group selector gates SMA through SMI. The number group selector gates SMA through SMI select the particular number group access address register by coincident gating with the coded thousands digit.

With the number group selector gates enabled, the units, tens, and hundreds access gates (ZUAl through ZHDl) for the addressed number group are likewise enabled, and the dialed units, tens and hundreds digits are registered in the access address register flip-fiops (ZUA-FF group ZUAR through ZHD-FF in group ZHAR).

Common drum location address circuit The complete drum location address circuit is essentially four binary counters; (l) a 4 stage binary counter ZBC to generate the time slots TSA through TSD shown on correspondingly marked leads. These time slots are used for gating the 4 words of translated information to the correct exit buffer registers during read out; (2) a l0 stage units counter ZUC; (3) a 10 stage tens counter ETC; and (4) a l0 stage hundreds counter ZHC. Each index pulse ILP advances the 4 stage binary counter one count. On the fourth count the units counter is advanced by the index pulse 1P and coincidence with the TSD pulse of the 4 stage binary counter 213C at AND gate ZCG. For every l0 counts of the units counter, the tens counter is advanced, and for every counts of the tens counter the hundreds counter is advanced. After 1000 counts all the counters are set to zero by the reset index pulse ZRS. Therefore, the drum index pulses present `a new address number in the counter every 33 as. and also generate 4 time slots of 8.25 as. eachV for every address.

Coincidence circuit To detect arrival of the drum at the location desired by the dialed digits received from the transceiver and stored in the access address register composed of units digit storage ZUAR, tens digit storage ZTAR and hundred digits storage ZHAR, coincidence must be detected between the binary code representation in the flip-fiop such as ZUA-FF, ZUB-FF, @UC-FF and ZUD-FF of the units digit storage for the dialed digits and the binary code representation of the drum location address appearing in the counters ZUC, ZTC and ZHC. The coincidence circuit consists of `an AND gate for each output state of the register fiip-fiops. One AND gate 2U for the one output and one AND gate 2U for the not output. These two outputs are checked for parity against similar outputs from the counters. Upon parity the OR gate ZUY marks on the input lead to the units coincidence AND gate ZUCG for the units digit. The coincidence gates continuously compare the register outputs with the counter outputs and when coincidence of all digits Occur, the complete address number coincidence gate ZNC is enabled, and the 2CP1 lead becomes true. This signal 6 signifies that the drum has reached the addressed location and thc translated information can now be read out.

Translated information read out and exit bujer storage circuits The translated information appears as 6 digits each stored in a sequential 4 bit binary code. As the information is read out it must be stored until the transceiver can return to the number group to receive the translated information. The buffer storage necessitates 4 ip-fiops per digit with the time slot access gates to convert the sequentially appearing information to parallel fiip-fiop storage.

'This is done by sequentially gating the output of each read amplifier to the designated flip-flop. In more detail, time slots TSA through TSD are multiplied to sequence gates 3SA1-3SD1 for the rst digit and so on through 3SA6-3SD6 of the sixth and final digit.

Hence, upon coincidence and appearance of CP1 to all sequence gates, the information stored in the digit 1, first time slot position is gated with TSA at the 3SA1 gate and used to set the SRAl-FF; one At the same time the information in digit 2, first time slot position, is gated with TSA at a similar gate and used to set a similar flipiiop one and so on through digit 6. 8.25as. later TSB is true and information at the digit 1 second time slot position, through digit 6 second time slot position is gated at 3SB1 through 3SB6 respectively and used to set ipfiops SRBl through 3RB6 respectively to the one state.

The translated information is stored in the exit buffer register flip-flops (SRAl-FF through 3RD6-FF) until the transceiver is finished with it and initiates a reset pulse to reset all the exit bufier register flip-Hops 3RA1 through 3RD6 and also the access address register flip-flops ZUA in group ZUAR through 2HD in group ZHAR.

Since the time slot in which the transceiver comes back to the number group is not synchronized with the information read-out time of the drum, the exit highway for the exit buffer-register flip-flops SRAI through 3RD6 must be inhibited until all the information is read from the drum into these register flip-flops. This can be assured if CP1, indicating coincidence, is gated with the end of TSD, indicating reading completed, and then used to set a. llip-iiop in the control circuit. Then every time the transceiver comes back to the addressed number group through the number group selector gates SMA through SMT, an AND gate will be enabled, which in turn will enable AND gates SEAT through 3ED6 to put the information stored in the exit buffer registers onto the exit common highway to the transceiver via OR gates SWAT through 3WD6.

Busy circuit (ANI) When a register sender group transceiver requires service from the ANI circuit, it must first ascertain whether the ANI circuit is idle. This is done by coincident gating of the interrogation signal from the transceiver via lead 5BT. If the ANI circuit is idle, a gate will be enabled. The output of this gate, coupled through an OR gate BYN, will set a busy flip-flop to the one state, indicating the ANI circuit is busy, and inhibiting any other transceiver from seizing this ANI circuit. When the transceiver is finished, a release signal is coupled through to set the busy flip-flop to the zero or idle state, to present an output on the reset lead SRST. A time out circuit is enabled when the busy fiip-fiop is set to the busy state and, after a set period of time, it overrides the transceiver and sets the busy iiip-flop back to idle.

Register sender transceiver ANI connecz'ng circuit Since the transceiver cannot obtain its information from the ANI circuit within the initial time slot, it must continually return until the information is available. To do this, a one bit storage is necessary in the transceiver to remember lthat the ANI circuit has been tested, found idle and seized. When the busy fiip-op is set busy, the output is gated with the time slot of the transceiver annessa connected to the common highway at that time, and used to set the transceiver seizure lip-liop to the one state. Since the seizure ip-ilop is common to a transceiver group, it is handled on a 4time division multiplex basis with storage per transceiver. The seizure flip-ilop is released (set zero) either by a release signal from the transceiver or by a Time-Out circuit.

Access register circuit After a transceiver obtains the services of the ANI circuit, it must transfer and store the information for comparison with the information stored on the drum. Since the highways from the transceiverV groups are on a time division multiplex basis, gating of the highway information must occur only after verified seizure of the ANI circuit and during the time slot assigned to the particular transceiver. The one output of the transceiver seizure flip-op signifying seizure, is gated with the proper transceiver time slot to enable gate SSGS. T he output of gate SSGS is gated with the coded highway information (gates GAI-GD@ to set access register iiipflops GA1-FF GD-FF).

The four stage binary counter 4C provides a space and time separated series of four pulses of about 35 ms. width. They are used to gate, sequentially, the heads at 5DGA1 through SDGFI@ of the proper drum toV the proper coincidence'cireuit 4CC, to gate, sequentially, the time slots TSA-TSD from the individual drums Vto the common time slot leads, CSA-CSD, and to gate (at coincidence) the output of the drum address counters ZUC, ETC and ZHC of the proper drum to the exit registers dUR, ATR and Ltrl-IR. In addition, the output on the leads, CA-CD, indicating which drum is being interrogated is coupled through the gate 4D1-4D4, to set one of the ip-ops of register 4DR, to indicate in which drum coincidence occurred. This is the directory ten-thousands digit.

Coincidence circuit A separate coincidence circuit is required for each segment of the iirst drum to a maximum of ten. The segments of each additional drum are multipled to'the proper coincidence circuit via gates 5CGA1-5CGF10.

The condition of the access registers, SGA1-5GD6, is gated by the common time slots ythrough the proper gates (YAl in group 41.1 to YD() ingroup 4L6, NAI in group fs-L1 to N136 in group 41.6 and Y1 inrgroup SLI to Nd in group 4L6) to all the coincidence circuits; bit one of all six digits during time slot CSA and bits two, three and four during time slots CSB, CSC, and CSD, respectively.Y The output of the proper drum is read out by the heads and gated toV input leads 5V1-SV6 of the coincidence circuit 4CC (4CC is shown asa box for simplicity and is similar to the circuit disclosed for ZUCG), each segment beingV connected to a separate coincidence circuit. The first bit of Vall six digits is read out from both the drum and the access register during time slot CSA, the second during tim-e slot CSB, etc. Invertersare used to obtain a zero and one condition for each bit. VThe zero condition from any access register iiip-op is compared with the one condition of lthe corresponding drum bit by gates in the coincidence circuit. If any one of the 24 bits in theY six digit number in the access register is diiierent than the information on the drum,fa gate is enabled and the coincidence flip-flop is set to the one condition. Y

If, at the end of time'slot CSD, the coincidence flipop in any coincidence circuit'isrstill set zeroj7 another coincidence gate is enabled and an output appears on one of the ten leads YSCGl-il, to indicate in which segment coincidence occurred. This -is the directory thousands digit. incidence circuit is set back to Zero at the beginning of each CSA time slot so that the-next 24 bits can be A coincidence iip-fiop in the co-V Y checked for coincidence.

If coincidence is not found in a period of time needed to cover a complete revolution of the drum, (about 35 ms.) the 4-stage binary counter @C will advance to the next drum selecting lead CA-CD and the next drum will be checked in the sarne way.

Exit Registers If coincidence occurs, an output on any SCGI-ll) lead will be gated with the zero output of a flip-flop in the control circuit to give an output on the system coincidence lead SC and set this ip-tlop to one The removal of the zero output from this flip-Hop inhibits a gate. The result is a short pulse on the SC lead when coincidence lirst occurs. If all four drums are scanned and the cycle begins again, the re-occurrence of coincidence will not cause another pulse on lead SC. The pulse on lead SC is used to gate the directory units, tens, hundreds, thousands (drum segment), and tenthousands (one of four drums) digits to the exit register ilip-ops ffUR, dTR, 4HR, riMR and 4DR respectively. The output leads of these flip-flops make up the highway to the transceiver group. Both the input and output highways to the transceiver groups are so controlled that only one transceiver can give and receive information to an ANI circuit at any time. When the transceiver is finished, a release signal is sent to the ANI circuit which resets all Vflip-hops. This makes the ANI circuit idle and prepares it for the next call.

While the principles of the invention have been described above in connection with specific embodiments, and particular modifications thereof, it is to be clearly understood that this description is made only by way of example and not as a limitation on the scope of the invention.

\Vhat is claimed is:

l. In an automatic telephone system including registersenders, a calling Vone of said register-senders, a common translator arranged to provide call routing information or subscriber directory number information to said register-senders, and a translator allotter operated to connect said calling one of said register-senders to said translator, said translator including; a first plurality of register means operated to register the called directory digit data from said register-sender, a second plurality of register means operated upon receipt of calling subscriber equipment identity digits, a constantly rotating magnetic drum record means having recorded therein a plurality of sets of coded call routing and control data items, record reader means continuously scanning `said record means, first output register means, second output register means, counter means arranged toin-dicate the address of said reader means in relation to said record means, lirst coincidence Vmeans continuously electrically operated to compare call routing data of the registered signals in said first incorning register means with the output address count of said counter means, second coincidence means and coincidence gating means including means responsive to receipt of information in said second register means to extend the outputs of said record reader means comprising the directory digits corresponding to said equipment identity digits to said second coincidence means, gating means responsive to correspondence of the called directory digitdata and said counter means address count output in said first coincidence means for passing the outputs of said record reader means to said iirst output register means for transmission to said register-senders, and other means responsive to correspondence of the calling subscriber equipment identity code in said 'second register means and said reader means output to extend said counter address indication to said second output register means.

2. In an automatic telephone system including registersenders, a calling one of said register-senders, a common translator arranged to provide call routing information or subscriber directoryr number information to said registersenders, and a translator allotter operated to connect said calling one of said register-senders to said translator, said translator including; a first plurality of three incoming directory digit register means for registering the digits of a three digit code from said register-sender, four conductors for each code, each register having a first and a second set of four conductors and responsive to registration therein of a digit to establish different potentials on said first and said second set of conductors according to the registered digit, a second plurality of calling subscriber equipment identity register means, constantly rotating magnetic drum record means having recorded therein a plurality of `sets of coded call routing and control data items, record reader means continuously scanning said record means, a first plurality of output register means, `second output register means, counter means arranged to indicate the address of said reader means in relation to each said record means in a four bit code, first coincidence means continuously electrically operated to compare call routing data of the registered signals on each of said two sets of conductors with the address count outputs of said counter means, second coincidence means and coincidence gating means including means responsive to receipt of information in said second register means to extend the outputs of said record reader means comprising the directory digits corresponding to said equipment identity digits to said second coincidence means, gating means operated responsive to correspondence of the called directory digit data and said counter means output in said first coincidence means for passing the outputs of said record reader means to one of said first plurality of output register means, and other means responsive to correspondence of the calling subscriber equipment identity code in `said second register means and said reader means output to extend said counter address indication to said second output register means.

3. In an automatic telephone system including registersenders, a calling one of 'said register-senders, a common translator arranged to provide call routing information or subscriber directory number information to said registersender, and a translator allotter operated to connect said calling one of said register-senders to said translator, said translator including; -a first plurality of register means, a second plurality of register means for registering the digits in a code via four conductors for each code, each register having a first and a second set of four conductors and responsive to registration therein of a digit to establish different potentials on said first and said second set of conductors according to the registered digit, a constantly rotating magnetic drum record means having recorded therein a plurality of sets of coded call routing and control data items in a four bit sequential code, record reader means continuously scanning said record means whereby said recorded data establishes four sequential bits of information on a single lead for each digit read, a series of four gates connected to said single lead, first output register means, second output register means, counter means arranged to indicate the address of said reader means in relation to said record means and to produce a four unit series of gating pulses, rst coincidence means continuously electrically operated to compare call routing data of the registered signals with the `outputs of said counter means, intermediate buffer storage means consisting of a filip-dop for each bit of information of a code and connected one to each of said four gates, said four gates sequentially enabled by said four unit series of gating pulses from said counter, second coincidence means and coincidence gating means including means responsive to receipt of information in said second register means to extend the outputs of said intermediate buffer storage means to said second coincidence means, gating means responsive to correspondence ofthe called directory digit data and said counter output means in said first coincidence means for passing the outputs of said record reader means to said first output register means, and other means responsive to correspondence of the calling subscribed equipment identity code in said second register means and in said buffer storage means output to extend said counter address indication to said second output register means.

4. In an automatic telephone system including registersenders, a calling one of said register-senders, a common translator, and a translator allotter operated to connect said calling one of said register-senders to said translator, said translator including: a first and a second plurality of incoming register means, a constantly revolving magnetic drum record means having recorded therein a plurality of sets of coded call routing and control data items, record reader means continuously scanning said record means, a first and a second output register means, counter means arranged to indicate the address of said reader means in relation to said record means, a first and a second coincidence means, said first coincidence means continuously electrically operated to compare call routing data of the registered signals in said first incoming register means with the address count output of said counter means, and first and second gating means, said first gating means operated to pass the outputs of said record reader means to said first output register means in response to said first coincidence means finding correspondence of the call routing data and said counter output means address output, said second coincidence means including means responsive to receipt of information in said second register means to continuously compare the output signals of said record reader means with data in said second register means, said second coincidence gating means responsive to correspondence of the items in said second register means and the output signals of said record reader to extend said counter address indication to said second output register means.

References Cited bythe Examiner UNITED STATES PATENTS 2,851,534 9/58 Bray et al 179--7 2,891,113 6/59 Flood 179-18 2,973,511 2/ 61 McLaughlin 179--18 3,032,747 5/62 French v179--18 ROBERT H. ROSE, Primary Examiner.

WALTER L, LYNDE, Examiner. 

1. IN AN AUTOMATIC TELEPHONE SYSTEM INCLUDING REGISTERSENDERS, A CALLING ONE OF SAID REGISTER-SENDERS, A COMMON TRANSLATOR ARRANGED TO PROVIDE CALL ROUTING INFORMATION OR SUBSCRIBER DIRECTORY NUMBER INFORMATION TO SAID REGISTER-SENDERS, AND A TRANSLATOR ALLOTTER OPERATED TO CONNECT SAID CALLING ONE OF SAID REGISTER-SENDERS TO SAID TRANSLATOR, SAID TRANSLATOR INCLUDING; A FIRST PLURALITY OF REGISTER MEANS OPERATED TO REGISTER THE CALLED DIRECTORY DIGIT DATA FROM SAID REGISTER-SENDER, A SECOND PLURALITY OF REGISTER MEANS OPERATED UPON RECEIPT OF CALLING SUBSCRIBER EQUIPMENT IDENTITY DIGITS, CONSTANTLY ROTATING MAGNETIC DRUM RECORD MEANS HAVING RECORDED THEREIN A PLURALITY OF SETS OF CODED CALL ROUTING AND CONTROL DATA ITEMS, RECORD READER MEANS CONTINOUSLY SCANNING SAID RECORD MEANS, FIRST OUTPUT REGISTER MEANS, SECOND OUTPUT REGISTER MEANS, COUNTER MEANS ARRANGED TO INDICATE THE ADDRESS OF SAID READER MEANS IN RELATION TO SAID RECORD MEANS, FIRST COINCIDENCE MEANS CONTINUOUSLY ELECTRICALLY OPERATED TO COMPARE CALL ROUTING DATA OF THE REGISTERED SIGNALS IN SAID FIRST INCOMING REGISTER MEANS WITH THE OUTPUT ADDRESS COUNT OF SAID COUNTER MEANS, SECOND COINCIDENCE MEANS AND COINCIDENCE GATING MEANS INCLUDING MEANS RESPONSIVE TO RECEIPT OF IN- 